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Selective Address Compare

IP.com Disclosure Number: IPCOM000076863D
Original Publication Date: 1972-May-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

VanSchaack, KE: AUTHOR

Abstract

Execution of an internal program may involve references by various elements to the same address in main storage. Selective address compare provides the capability to examine a particular storage location on each occasion that it is accessed or only when it is accessed by a particular element.

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Selective Address Compare

Execution of an internal program may involve references by various elements to the same address in main storage. Selective address compare provides the capability to examine a particular storage location on each occasion that it is accessed or only when it is accessed by a particular element.

The selective address compare uses internal timing cycles which are generally available as part of the system hardware design.

Various separately controlled elements may generate a request for use of storage. Multiusers of storage are then priority timed.

The timing cycles for each element initiate the normal sequence of controls necessary for generating an address for the storage address register SAR. SAR specifies the address to be used in main storage MS and provides an output which is compared to address keys by address compare logic. Cycle selection gates, under control of the address compare mode rotary switch, gate only the selected storage cycle to the address compare logic. When the address key configuration compares to the SAR address, a signal may be generated for a syncing reference or for halting system operation.

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