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Instruction Sequencing Control

IP.com Disclosure Number: IPCOM000076864D
Original Publication Date: 1972-May-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 6 page(s) / 64K

Publishing Venue

IBM

Related People

Beebe, BO: AUTHOR [+8]

Abstract

INTRODUCTION. In a data-processing system which includes two execution units (an A-unit and an X-unit), instruction execution occurs in four relatively distinct phases: I) the movement of the instruction from storage to a buffering region; II) the initial decoding of the instruction and the dispatching of it to either the A-unit or the Xunit; the final decoding of the instruction and its interlocking to insure the readiness of the operands and facilities required by it; and IV) the actual computation indicated by the instruction.

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Instruction Sequencing Control

INTRODUCTION.

In a data-processing system which includes two execution units (an A-unit and an X-unit), instruction execution occurs in four relatively distinct phases: I) the movement of the instruction from storage to a buffering region; II) the initial decoding of the instruction and the dispatching of it to either the A-unit or the X- unit; the final decoding of the instruction and its interlocking to insure the readiness of the operands and facilities required by it; and IV) the actual computation indicated by the instruction.

The processing of instructions in phases I and II is discussed below. This includes the prefetching of instructions, the control of the order in which they are decoded and the effect of branch instructions. Fig. 1 schematically indicates the facilities encompassed by phases I and II.

Instructions are contained in storage in 192-bit sets (an instruction word). An individual instruction is either 24 or 48 bits; thus one instruction word may contain from four to eight instructions. The set is processed as an entity during phase I and part of phase II. In the remainder of phase II (and in phases III and IV) the processing is on an individual 24- or 48-bit instruction.

Although 192-bit sets are used in phase I, there are no programming constraints for alignment of individual instructions within an instruction word. In particular; a branch may be made to any addressable location, and 48-bit instructions may overlap two instruction words.

Referring to Fig. 1, the normal path of instruction words through phases I and II is as follows. An instruction word is fetched from storage and held in one of twelve instruction buffers IB along with the storage address from which it came. This fetch is normally made in advance of the specific requirement for it, and it will be available in an IB when it is required. From the IBs the instruction word passes through an A-unit predecoder to one of two A-unit dispatch registers. The same instruction word passes through an X-unit transmission. The predecoding process identifies the beginning of each individual instruction, any exit instructions, and the unit (A- or X-unit) to which each instruction is to be forwarded.

A scan and dispatch mechanism then transfers instructions to the A- and X- units for execution.

The control of phases I and II is implemented by two tables (the history table and the decoding order table), three address registers (the next fetch address NFA, effective branch address EBA, and next sequential address NSA registers), and a set of eight prefetch sequence control registers PSC. In general, the next fetch address register contains the address of the next instruction word to be prefetched from storage, and the history table indicates into which buffer the instruction word is to be placed. The effective branch address register contains the address of the next instruction word to be decoded after the resolution of a

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