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System for Interlocking Between Asynchronously Operating Indexing and Arithmetic Units

IP.com Disclosure Number: IPCOM000076873D
Original Publication Date: 1971-Jul-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 4 page(s) / 55K

Publishing Venue

IBM

Related People

Homan, ME: AUTHOR [+2]

Abstract

In a single-instruction-counter machine with numerous execution units such as adders, shifter, or multipliers, high performance can be achieved only if a relatively large number of instructions can be decoded simultaneously and can be executed simultaneously . In order to accomplish this, and referring to I, the instruction stream 1 is divided into two semiindependent streams at an early stage of decoding. These streams are the addressing or index (X) stream 3 and the arithmetic (A) stream 5. Each stream is associated with its own set of execution units and data registers, as in the X addressing unit 7 and the A arithmetic unit 9. Memory 11 supplies data to the A arithmetic unit from addresses supplied by the X addressing unit.

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System for Interlocking Between Asynchronously Operating Indexing and Arithmetic Units

In a single-instruction-counter machine with numerous execution units such as adders, shifter, or multipliers, high performance can be achieved only if a relatively large number of instructions can be decoded simultaneously and can be executed simultaneously . In order to accomplish this, and referring to I, the instruction stream 1 is divided into two semiindependent streams at an early stage of decoding. These streams are the addressing or index (X) stream 3 and the arithmetic (A) stream 5. Each stream is associated with its own set of execution units and data registers, as in the X addressing unit 7 and the A arithmetic unit 9. Memory 11 supplies data to the A arithmetic unit from addresses supplied by the X addressing unit.

Some instructions, such as loads of A-unit registers, transmitting from A to X registers, and arithmetic setting of condition code bits affect both streams of instructions. Much of the benefit of splitting the original instruction stream is lost if each line of A and X instruction buffers must interlock with every other line in the two buffers, or when both parts of a compound instruction must be executed simultaneously. The present scheme provides a simple, inexpensive method for maintaining the essential order of the original instruction stream without line-by- line interlocking or resynchronization. It also allows the system to issue a second load command to a destination register R/1/, while data from a previous memory request to load the same register is still in transit. Furthermore, it is permissible for the memory to return to second load data ahead of the first load data. This is a natural characteristic of memory systems which consist of multiple units, some of which may be busy with other requests.

In general, load instructions, which are a subset of X unit instructions are sent to the X unit, and their counterparts in abbreviated form, called Replace, are sent to the A unit. A Replace instruction marks the position of the Load in the arithmetic instruction stream and specifies the register, hereinafter referred to as R/1/, being load in the A unit 9. Each register R/1/ in the arithmetic unit has associated therewith a load buffer LB/1/. If R/1/ is empty and a valid candidate for receiving data, it will be filled by data from memory or from LB . If R/1/ is not empty, data can be temporarily stored in LB/1/ for subsequent transfer to R/1/. Associated with the R/1/-LB pair are a group of control bits. These control bits in- include Busy bits B, which indicate that LB/1/ is busy. There are two Busy bits for each R/1/-LB/1/ pair. The Pass bit P for LB/1/ indicates that data can bypass the load buffer and be gated directly to R/1/. The Wait bit W/1/ indicates that R/1/ is waiting to be filled with the results of an instruction currently in the process of execution. The instruction may be an arithmetic instruction or...