Browse Prior Art Database

System for Interlocking between Asynchronously Operating Indexing Arithmetic Units

IP.com Disclosure Number: IPCOM000076874D
Original Publication Date: 1971-Jul-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 3 page(s) / 56K

Publishing Venue

IBM

Related People

Freiman, CV: AUTHOR [+4]

Abstract

In a single-instruction-counter machine with numerous execution units such as adders, shifter, or multipliers, high performance can be achieved only if a relatively large number of instructions can be decoded simultaneously and can begin execution simultaneously. In order to accomplish this, and referring to I, the instruction stream 1 is divided into two semiindependent streams at an early stage of decoding. These streams are the addressing or indexing (X) stream 3 and the arithmetic (A) stream 5. Each stream is associated with its own set of execution units and data registers, as in the X addressing unit 7 and the A arithmetic unit 9. Memory 11 supplies data to the A arithmetic unit for addresses supplied by the X addressing unit.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 3

System for Interlocking between Asynchronously Operating Indexing Arithmetic Units

In a single-instruction-counter machine with numerous execution units such as adders, shifter, or multipliers, high performance can be achieved only if a relatively large number of instructions can be decoded simultaneously and can begin execution simultaneously. In order to accomplish this, and referring to I, the instruction stream 1 is divided into two semiindependent streams at an early stage of decoding. These streams are the addressing or indexing (X) stream 3 and the arithmetic (A) stream 5. Each stream is associated with its own set of execution units and data registers, as in the X addressing unit 7 and the A arithmetic unit 9. Memory 11 supplies data to the A arithmetic unit for addresses supplied by the X addressing unit.

Some instructions, such as load of A-unit registers, transmitting from A to X registers, and arithmetic setting of condition code bits affect both streams of instructions. Much of the benefit of splitting the original instruction stream is lost if each line of A and X instruction buffers must interlock with every other line in the two buffers, or when both parts of a compound instruction must be executed simultaneously. The present scheme provides a simple, inexpensive method for maintaining the essential order of the original instruction stream without line-by- line interlocking or resynchronization.

In general, load instructions which are subset of X-unit instructions are sent to the X unit, and its counterpart in abbreviated form, called Replace, is sent to the A unit. A Replace instruction marks the position of the Load in the arithmetic instruction stream and specifies the register, hereinafter, referred to as R/i/, being loaded in the A unit 9. Each register R/i/ in the arithmetic unit has associated therewith a load buffer LB/i/. R/i/ is empty and a valid candidate for receiving data, it will be filled by data from memory. If R/i/ is not valid, data can be temporarily stored in LB for subsequent transfer to R/i/. Associated with the R/i/-LB pair are a group of control bits. These control bits are: W/i/- The Wait bit indicates that R/i/ is waiting to be loaded

by an instruction currently in the process of execution.

p/i/- The Pass bit for LB/i/ indicates that data may bypass the

buffer and be gated directly to R/i/.

B/i/- The Busy bit for LB indicates that the load buffer is

currently busy.

F/i/- The Full bit for LB/i/ indicates that the load buffer is

currently full.

Operation is as follows. Referring to II, a load instruction destined to load register R/i/ with a particular data word enters the X instruction stream 3. The X unit tests the busy bit B for LB/i/ at 13. If the busy bit is a 1, it indicates that the load buffe...