Browse Prior Art Database

Variable Pessimism with a Three Value Unit Delay Logic Simulation

IP.com Disclosure Number: IPCOM000076875D
Original Publication Date: 1971-Jul-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 3 page(s) / 66K

Publishing Venue

IBM

Related People

Vogelsberg, RE: AUTHOR

Abstract

During the design verification of a large sequential machine, an unknown value (X) can be used in addition to the binary levels (1 and 0) to detect race or hazard conditions within the logic. This may be accomplished by preceding input value transitions with variable duration transitions to X independent of the machine timing cycle. This hazard detection capability (hereafter referred to as variable pessimism) can be provided in a unit delay simulator. During a unit delay simulation two working lists or stacks are normally used to propagate logic activity. At any given time one stack contains the list of logic blocks to be calculated. This list is processed, new values are calculated for the blocks in the stack, and these values are saved in a temporary location.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 3

Variable Pessimism with a Three Value Unit Delay Logic Simulation

During the design verification of a large sequential machine, an unknown value (X) can be used in addition to the binary levels (1 and 0) to detect race or hazard conditions within the logic. This may be accomplished by preceding input value transitions with variable duration transitions to X independent of the machine timing cycle. This hazard detection capability (hereafter referred to as variable pessimism) can be provided in a unit delay simulator. During a unit delay simulation two working lists or stacks are normally used to propagate logic activity. At any given time one stack contains the list of logic blocks to be calculated. This list is processed, new values are calculated for the blocks in the stack, and these values are saved in a temporary location. When all the entries in the stack have been calculated, the stack is processed a second time. these values are saved in a temporary location. When all the entries in the stack have been calculated, the stack is processed a second time. During the second processing of the stack the values of any logic blocks that have changed are updated, and any logic blocks fed by these blocks are placed in the next stack. When the updating is completed, the simulator time is incremented by one unit, the roles of the two stacks are switched, and the simulation is continued. During this process, primary input changes are treated like logic block value changes.

As seen in the flowchart, a three-value unit delay simulation may be modified to include the variable pessimism capability by the addition of two working lists to the simulator. When a primary input change occurs, instead of immediately propagating the new value, the primary input is set to X and the effect of the X is propagated using the two additional stacks. During this propagation the simulator time is not incremented. Changes in block values are updated in a normal fashion during the propagation. When the desired number of levels of unknown propagation is reached, the final calculation and update of values causes any pending calculations to be placed in the normal stacks. The primary input value changes (which have been saved) are entered in the normal stacks. The simulation then continues, using the normal stacks and incrementing the si...