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Data Threshold Circuit

IP.com Disclosure Number: IPCOM000076877D
Original Publication Date: 1971-Jul-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Croisier, A: AUTHOR [+2]

Abstract

The circuit detects information above a threshold level which is a fraction of its peak amplitude. It is used for differentiating between a 1 and a 0 applied to its input terminal. An input signal containing both polarities is rectified in a full-wave rectifier comprising two matched transistors T1 and T2. The base electrode of each receives the true signal and the inverted signal respectively. The two emitter electrodes are connected to capacitor C1 by an amplifier stage. This stage is provided with transistor T3 the output load of which consists of resistor RL connected to its emitter. C1 stores the peak amplitude of the rectified input signal. A fraction of such peak amplitude is obtained by resistors R1 and R2 which are connected in series between emitter of transistor T3 and ground.

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Data Threshold Circuit

The circuit detects information above a threshold level which is a fraction of its peak amplitude. It is used for differentiating between a 1 and a 0 applied to its input terminal.

An input signal containing both polarities is rectified in a full-wave rectifier comprising two matched transistors T1 and T2.

The base electrode of each receives the true signal and the inverted signal respectively. The two emitter electrodes are connected to capacitor C1 by an amplifier stage. This stage is provided with transistor T3 the output load of which consists of resistor RL connected to its emitter. C1 stores the peak amplitude of the rectified input signal. A fraction of such peak amplitude is obtained by resistors R1 and R2 which are connected in series between emitter of transistor T3 and ground. This fraction of peak amplitude is taken from the point common to R1 and R2 and is smoothed by capacitor C2 connected in parallel with R2. The voltage between terminals of C2 is the threshold value of the circuit. It is applied to one input terminal of a differential amplifier DA, the second input terminal of which receives from the emitters of T1 and T2 the full-wave rectified input signal. The advantage of this circuit is the balancing of the drift of the characteristics of the transistors.

This balance is obtained in the differential amplifier stage.

Voltage A delivered by the rectifier is given by: A = absolute value of V - VD where absolute value of V...