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Write Once Addressing of Redundant Lines in a Monolithic Memory Chip

IP.com Disclosure Number: IPCOM000076880D
Original Publication Date: 1972-Apr-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Gates, HR: AUTHOR [+2]

Abstract

In a monolithic memory array where there is a redundant number of bit lines, e.g. one extra bit line which is to be permanently and selectively eliminated from the array, there is provided an approach which will accomplish this result by an input combination of a plurality of fusible elements.

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Write Once Addressing of Redundant Lines in a Monolithic Memory Chip

In a monolithic memory array where there is a redundant number of bit lines, e.g. one extra bit line which is to be permanently and selectively eliminated from the array, there is provided an approach which will accomplish this result by an input combination of a plurality of fusible elements.

In the Figure, the input lines 10 to exclusive OR (XOR) 11 may be used to select one of the nine bit lines 12 (8+1 redundant line) which is to be permanently eliminated. One or more of fusible diodes 13 is selectively fused so as to fix the corresponding input 10 at ground level. The combination of inputs 10 at ground level will be decoded via the XOR 11 so that a signal is provided on one of the outputs 12 to one of the bit lines, which will permanently inhibit the bit line.

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