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Monolithic Storage Cell with FET's

IP.com Disclosure Number: IPCOM000076898D
Original Publication Date: 1972-May-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Baitinger, U: AUTHOR [+5]

Abstract

The storage cell consists of two cross-coupled cell transistors T1, T2 and the associated load transistors T5, T6 forming a flip-flop. Via the load transistors connected to bit lines Bl, B2 and controlled via gate line GL, the capacities whose opposed charged state indicates the stored information and which are arranged between cell coupling points V1, V2, respectively, and the substrate are recharged to compensate leakage currents.

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Monolithic Storage Cell with FET's

The storage cell consists of two cross-coupled cell transistors T1, T2 and the associated load transistors T5, T6 forming a flip-flop. Via the load transistors connected to bit lines Bl, B2 and controlled via gate line GL, the capacities whose opposed charged state indicates the stored information and which are arranged between cell coupling points V1, V2, respectively, and the substrate are recharged to compensate leakage currents.

To avoid stability and sensitivity problems, the read current is not fed via cell transistors T1 and T2, reading being rather electrically separated from writing. To this end, two serially connected transistors T3, T7 and T4, T8, respectively, are incorporated between each bit line B1, B2, respectively, and the reference potential. Each of the serially connected transistors T3, T4 connected to bit line B is linked, via the gate, with word line WL, whereas each of the serially connected transistors T7, T8 is connected, via the gate, to the associated cell transistor T1, T2, respectively.

For the description of the individual operations it is assumed that N-channel enhancement type field-effect transistors are used.

In the stand-by state, a low potential of word line WL inhibits transistors T3 and T4. The sufficiently high potential of gate line GL causes T5 and T6 to be made slightly conductive. The storage charge, decreased as a result of stray currents, is replenished from bit lines B1 and B2 whose potential is appropriately high.

During reading the potential of gate line...