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Dynamic FET Half Cycle Delay Coincidence Circuit

IP.com Disclosure Number: IPCOM000076903D
Original Publication Date: 1972-May-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Pi, SC: AUTHOR

Abstract

The basic coincidence circuit indicates both inputs are at the same logic level. A circuit which performs this function in a device which is small in size and has a comparatively small amount of interior winding is shown in Fig. 1. This half-cycle delay coincidence circuit consists of one type N NAND circuit having an output G1, one type N+1 OR/ AND Invert circuit having inputs A, B, G1 and an output G2.

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Dynamic FET Half Cycle Delay Coincidence Circuit

The basic coincidence circuit indicates both inputs are at the same logic level. A circuit which performs this function in a device which is small in size and has a comparatively small amount of interior winding is shown in Fig. 1. This half-cycle delay coincidence circuit consists of one type N NAND circuit having an output G1, one type N+1 OR/ AND Invert circuit having inputs A, B, G1 and an output G2.

Fig. 2 shows a flow diagram of the circuit operation. At time N the left-hand circuit path is energized from source VDD charging distributed capacity at the link between the circuits. The left (NAND) circuit is dumped upon the occurrence of signals A and B during time N+1. The right-hand circuit path is energized at N+1 and is dumped upon the concurrence of a G1 level and signals A or B, at N+2.

Assume N equals phase 1 of a four-phase cycle and the inputs A and B are valid during phases 2 and 3. The output G2 is then valid at output sampling time phase 4. The Boolean function for G2 output is: F(o) = (A.B) . (A+B) = A.B + (A+B) = A.B + A.B.

This circuit can be used in random field-effect transistor (FET) circuit design, where circuit density and wireability are critical.

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