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Dynamic FET Half Cycle Delay Exclusive OR Circuit

IP.com Disclosure Number: IPCOM000076904D
Original Publication Date: 1972-May-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Pi, SC: AUTHOR

Abstract

The basic exclusive OR circuit indicates that the output is "1" if either, but only one, of the inputs is 1 . A circuit which provides this function in a manner which saves delay time, and is characterized by relatively small device size and reduced interior wiring is shown in Fig. 1. This circuit consists of one type N NOR circuit, having an output H1, and one type N+1 AOI combination, having an input A, B, H1 and yielding an output H2.

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Dynamic FET Half Cycle Delay Exclusive OR Circuit

The basic exclusive OR circuit indicates that the output is "1" if either, but only one, of the inputs is 1 . A circuit which provides this function in a manner which saves delay time, and is characterized by relatively small device size and reduced interior wiring is shown in Fig. 1. This circuit consists of one type N NOR circuit, having an output H1, and one type N+1 AOI combination, having an input A, B, H1 and yielding an output H2.

Fig. 2 shows the logic flow in the operation of the circuit. The left-hand branch is energized from VDD at phase N and is de-energized upon the occurrence of A or B during phase N+1. The right-hand branch is energized at phase N+1 and is de-energized upon the occurrence of A + B during phase N+2.

If one assumes that N equals phase 1 of a four-phase cycle, and the inputs A and B are valid at phases 2 and 3, the output of H2 is valid at phase 4. The delay time is 1/2 cycle.

The circuit performs the positive exclusive OR function. The Boolean function for the output is: Fo = (A+B) + (A.B) = (A+B) . (A.B.) = (A+B) . (A+B) = AB + AB.

This circuit can be used in a random-logic system when wireability is critical.

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