Browse Prior Art Database

Reconfiguration System for Multiprocessor

IP.com Disclosure Number: IPCOM000076906D
Original Publication Date: 1972-May-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 3 page(s) / 52K

Publishing Venue

IBM

Related People

Albanes, NJ: AUTHOR

Abstract

In a multiprocessor, the multiple processing units can be configured all as part of one system or each as part of separate subsystems. A multiprocessor configurable into subsystems with a controlled degree of independence requires control over element state, element intercommunications and address translation. These features may be embodied in the configuration control units (CCU's), which in turn contain the controls and the necessary registers to provide this capability. The reconfiguration system described herein is a system used to load these registers and in turn to store their contents.

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Reconfiguration System for Multiprocessor

In a multiprocessor, the multiple processing units can be configured all as part of one system or each as part of separate subsystems. A multiprocessor configurable into subsystems with a controlled degree of independence requires control over element state, element intercommunications and address translation. These features may be embodied in the configuration control units (CCU's), which in turn contain the controls and the necessary registers to provide this capability. The reconfiguration system described herein is a system used to load these registers and in turn to store their contents.

The figure shows the configuration control system architecture that is utilized for the reconfiguration system. The elements of the input/ output controller (IOC), the central processing unit (CPU), and the main memory (MM) are those of a typical multiprocessor wherein multiported main memories are utilized. The configuration control units CCU consists of the address translation unit (ATU) and the communications state units (CSU) shown in the figure. The CCU load and store instructions are executed using a microinstruction control.

The configuration system makes use of "state 3", which is one of the element states. The function of state 3 is to impose on all other elements via external direct control an effective "stop".

While all elements except the "state 3 CPU" is under an externally imposed "stop" state, the state 3 computer under executive control proceeds to load each CCU's contents. The last to be loaded is the CCU of the state 3 CPU. This last loading takes place from the CPU's own scratchpad memory (SPM). Upon loading of its own communications state unit C/SU in the CCU of the state 3 CPU the externally imposed "stop" is removed.

On release from the "external stop" each CPU is then guided by its own CCU's contents. A CPU not configured to state 1, which is a stopped state, upon release will automatically go to preferential storage 0 for its first instruction. Each CPU has its own unique preferential storage address logical zero.

The reconfiguration system utilizes the storage data in and out paths normally found in a multiprocessor to load and store all CCU's, except for the load of the CCU of th...