Browse Prior Art Database

Detection of Phase Encoded Data

IP.com Disclosure Number: IPCOM000076920D
Original Publication Date: 1972-May-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Grombone, A: AUTHOR

Abstract

Limited phase encoded data is fed into the frequency discriminator (FD) circuit 10. The FD circuit discriminates against the high-frequency component of phase encoded data which corresponds to an all 1's or all 0's data pattern. No output is developed at this frequency.

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Detection of Phase Encoded Data

Limited phase encoded data is fed into the frequency discriminator (FD) circuit 10. The FD circuit discriminates against the high-frequency component of phase encoded data which corresponds to an all 1's or all 0's data pattern. No output is developed at this frequency.

When a change in binary state occurs in the phase encoded data, a low- frequency component is detected by FD circuit 10. This detected signal exhibits a peaking effect due to the low-frequency component detected. The polarity of this peak automatically indicates that the binary state has changed from a 0 to a 1 or vise versa, depending upon the phase encoded format used.

The output from FD circuit 10 is level detected by a wide hysteresis Schmitt trigger 12 and then logically combined in logic circuit 14 with phase encoded data to generate 0, 1, and clock information. In the logic circuit, "A" represents an AND gate, "0" represents an OR gate, and "1" represents an inverter. A phase delay circuit 16 is used to properly align the gating output with phase encoded data.

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