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Making Ion Implanted Self Aligned FET Using Silicide Metallurgy

IP.com Disclosure Number: IPCOM000076928D
Original Publication Date: 1972-May-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Fang, FF: AUTHOR [+3]

Abstract

In this method, Pd Si is used for field-effect transistor (FET) gate metallization and serves as a mask to prevent ion-implanted dopant from going into the channel region below the gate.

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Making Ion Implanted Self Aligned FET Using Silicide Metallurgy

In this method, Pd Si is used for field-effect transistor (FET) gate metallization and serves as a mask to prevent ion-implanted dopant from going into the channel region below the gate.

The FET devices are fabricated using standard processes of Si planar technology to the point shown in Fig. 1. A blanket layer of Si is then deposited (evaporation, chemical-vapor deposition) and delineated to the desired metallization pattern, using conventional photolithography and etching techniques to give the structure shown in Fig. 2. A layer of Pd is now deposited over the whole wafer, converting the polycrystalline Si layer to Pd Si. The unreacted Pd is then etched away with KI etchant which will dissolve Pd but not Pd Si. To complete the device, dopant is ion implanted to extend the source and drain regions to the edge of the channel. In Fig. 3, dopant is prevented from entering the channel region during the implantation by the Pd Si.

The use of Pd(2)Si as a gate metal/ion-implantation mask has several advantages for fabrication of micron and submicron devices. The requirements placed on the gate metal by the self-aligned gate process used to make high performance FET's include, (1) the metal must be thick enough to prevent the ion-implanted dopant from penetrating into the gate and (2) it must be thin enough to allow accurate etching of submicron lines. The thickness required of Al or Si, the gate materials,...