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Logic Circuits for Determining Branch Conditions

IP.com Disclosure Number: IPCOM000076966D
Original Publication Date: 1972-May-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Iskiyan, JL: AUTHOR [+3]

Abstract

Branching from an instruction stream is made conditional upon branch code and other signals generated in response to other general machine conditions.

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Logic Circuits for Determining Branch Conditions

Branching from an instruction stream is made conditional upon branch code and other signals generated in response to other general machine conditions.

An instruction-address register 11 has its contents normally stepped on by an instruction counter 23. When the instruction register 14 contains a branching code in the BR portion of the instruction word, or when branch condition signals are received from the other operating portions of the machine, then the instruction counter is inhibited by the disabling of AND gate 43. Under these conditions the address register 11 receives the modified address from either AND gate 40, passing a complete address contained in the previous instruction word, or specific bit positions of the address register are modified by signals received on lines 46 and 47 from logic blocks 18 or 19.

AND gate 40 is enabled by a signal from OR gate 44. This signal also acts to disable AND gate 43 through an inverter circuit 42. An address backup register 25 has a bit position, which indicates which zone of the two-zone control memory 10 supplied the current instruction word. Depending upon which zone supplied the word, register 25 through line 26 supplies a signal which enables the AND gates of logic block 18 through inverter circuit 30 or the AND gates of logic block
19. The logic blocks also receive input from the other operating portions of the machine, shown in the diagram as functions A=+, A=0;...