Browse Prior Art Database

Cache Memory Address Method

IP.com Disclosure Number: IPCOM000076973D
Original Publication Date: 1972-May-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Mastranadi, JF: AUTHOR

Abstract

This method minimizes the interference rate between the central processing unit (CPU) and I/O for access to Cache Storage. The approach involves the use of a Cache Address Array Extension, which is interrogated by the I/O each time the I/O writes a word in Main Storage. The contents of the Address Array Extension are modified each time the main Cache Address Array is updated by the CPU. In this way the Address Array Extension always contains the same address tag identified as the Main Cache Address Array. If the Main Storage address presented by the I/O is contained in the Cache Address Array Extension, the I/O data word is stored in the indicated location in the Cache Data Array and in Main Storage.

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Cache Memory Address Method

This method minimizes the interference rate between the central processing unit (CPU) and I/O for access to Cache Storage. The approach involves the use of a Cache Address Array Extension, which is interrogated by the I/O each time the I/O writes a word in Main Storage. The contents of the Address Array Extension are modified each time the main Cache Address Array is updated by the CPU. In this way the Address Array Extension always contains the same address tag identified as the Main Cache Address Array. If the Main Storage address presented by the I/O is contained in the Cache Address Array Extension, the I/O data word is stored in the indicated location in the Cache Data Array and in Main Storage. If the Main Storage address is not contained in the Address Array Extension, the I/O data word is stored directly into Main Storage without interfering with the Main Cache Address Array or Data Array.

The figure shows the data flow for a Cache Storage System equipped with the Address Array Extension. The address of each I/O transfer to Main Storage is gated to the I/O Address Register (labeled block A). This address is then compared with the address tags stored in the Address Array Extension. If a NO COMPARE results, the I/O data word is written into the indicated Main Storage location. If the outcome of the comparison is a COMPARE, the low-order bits (the number of bits depend on the size of the Cache) of the address are used at the input...