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Sequentialization of Asynchronous Processors

IP.com Disclosure Number: IPCOM000076993D
Original Publication Date: 1972-May-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Bandat, K: AUTHOR [+2]

Abstract

In a multiprocessor system the use of common units, such as, main storage, global-data bus, etc., must be sequentialized so that at any given time only one of the processors is solely authorized, while the other processors are inhibited from using the common unit. Multiple simultaneous requests are resolved by a Request Resolution Unit RRU shown in the figure and incorporated in each processor. All RRUs are interconnected by two ring buses - "REQUEST" and "BLOCK". Distinction Unit DU causes all RRUs to behave differently, so that eventually only one processor is selected. At particular intervals which are different for each processor, the other processors reissue their requests until they are accepted.

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Sequentialization of Asynchronous Processors

In a multiprocessor system the use of common units, such as, main storage, global-data bus, etc., must be sequentialized so that at any given time only one of the processors is solely authorized, while the other processors are inhibited from using the common unit. Multiple simultaneous requests are resolved by a Request Resolution Unit RRU shown in the figure and incorporated in each processor. All RRUs are interconnected by two ring buses - "REQUEST" and "BLOCK". Distinction Unit DU causes all RRUs to behave differently, so that eventually only one processor is selected. At particular intervals which are different for each processor, the other processors reissue their requests until they are accepted.

A request from a processor appears on line ACTIVATE and sets RQ1. DU essentially comprises a counter, preset to n periods T via line SET-n, and a dedicated pulse generator started from RQ2. After n pulses the counter emits a signal. This signal sets Send Request monostable SRQ, to emit a request to the other RRUs via Other Request Detection unit ORD and the REQUEST bus, unless a request from another RRU or a blocking signal was received in the past time interval T. If in the subsequent period T after starting the request no request from another RRU is received, the RRU sets its flip-flop FR, activates the BLOCK line, to set monostable HBL in the other RRUs for one period T, and signals free to is processor. Monostables ORQ, HBL, and SRQ have a period T. In puts to SRQ and to A1 from SRQ are differentiated. Alternatively, if another request is sensed after a delay of n periods, with n being different for each DU, DU triggers further successive reque...