Browse Prior Art Database

Stop Instruction

IP.com Disclosure Number: IPCOM000077000D
Original Publication Date: 1972-May-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Davis, MI: AUTHOR [+2]

Abstract

This instruction allows the programmer to make a detailed checkout of a program, without the requirement for a great deal of overhead or code modification when the checkout is complete. The instruction is placed in the program at points selected for the purpose of analysis. In the normal mode, the instruction is treated as no operation ("no op") and the computer simply shifts to the next sequential instruction.

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Stop Instruction

This instruction allows the programmer to make a detailed checkout of a program, without the requirement for a great deal of overhead or code modification when the checkout is complete. The instruction is placed in the program at points selected for the purpose of analysis. In the normal mode, the instruction is treated as no operation ("no op") and the computer simply shifts to the next sequential instruction.

The drawing shows the hardware required to implement the instruction in a typical data-processing system having a main storage unit 1, storage cycle controls 2, an operation code register 3 and an operation decode unit 4. Under the influence of storage cycle controls 2, instructions are fetched from main storage unit 1 and loaded into the operation register 3. The instruction is interpreted by operation decode unit 4 to develop a signal indicating the nature of the instruction.

When a stop instruction is detected by the operation decode unit 4, a signal is developed on line 5 which is one of the inputs to AND gate 6. The other inputs to AND gate 6 are clock pulse C and a signal developed from key lock 7. When all inputs to AND gate 6 are conditioned, an output signal is transmitted through OR circuit 8 to turn on the stop state latch 9. The output signal from stop state latch 9 is applied through inverter 10, to fetch cycle request latch 11. Since this signal to the set input of the latch is low, it prevents the clock pulse D from setting...