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Switch Interconnection System with Varying Priority

IP.com Disclosure Number: IPCOM000077019D
Original Publication Date: 1972-May-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Bliss, BE: AUTHOR [+3]

Abstract

The illustrated interconnection system achieves nonblocking operation through the use of cyclically varying priority in the order of selection of scanned connection requests. Processor units P(0), P(1)..., P(N) (Fig. 1) interconnect for bidirectional data exchange with memory units M(0), M(1),...M(M) through identical N x M crosspoint switching arrays A(1), A(2); A(2) for processor unit to memory unit transfers and A(1) for memory unit to processor unit transfers. Controls CU receive connection requests from processor units, resolve priority on a cyclically varying basis and configure appropriate switch points in arrays A(1), A(2).

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Switch Interconnection System with Varying Priority

The illustrated interconnection system achieves nonblocking operation through the use of cyclically varying priority in the order of selection of scanned connection requests. Processor units P(0), P(1)..., P(N) (Fig. 1) interconnect for bidirectional data exchange with memory units M(0), M(1),...M(M) through identical N x M crosspoint switching arrays A(1), A(2); A(2) for processor unit to memory unit transfers and A(1) for memory unit to processor unit transfers. Controls CU receive connection requests from processor units, resolve priority on a cyclically varying basis and configure appropriate switch points in arrays A(1), A(2).

Considering the processor units as source requestors for transfer service thru A(2), their respective data functions SO(0) Data, SO(1) Data,... SO(N) Data (Fig.
2) are gated by respective scanning selection signals SEL SO(0),...SEL SO(N), which are established in a cyclically varying priority sequence, and OR'd to a single Memory Unit "Sink" input SK(m). The crosspoint controls (Fig. 3) receive source request functions SO(0) Req,...,SO(N) Req each including a sink address, decode the addresses, resolve request priorities and availability status of addressed (sink) units in priority logic units PL and configure appropriate connections to available sink units.

As shown in Fig. 4, each sink address SK(1) from a source requestor is decoded and applied to a gate conditioned by a correspond...