Browse Prior Art Database

Heat Dissipative Chip Carriers

IP.com Disclosure Number: IPCOM000077027D
Original Publication Date: 1972-May-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Goldman, OH: AUTHOR

Abstract

Chip carrier 1, shown in top elevation and side views in Fig. 1, has a bottom layer 3 of solid copper used to remove heat from a not shown integrated circuit, mountable upon chip attachment pad 5. This pad, of predominantly dielectric composition, includes heat conductive paths to the sink layer 3 formed through holes 7 lined by plated conductive material 9 (Fig. 2). If the heat dissipating layer 11 is selectively masked during formation of plated linings 9 it will be profiled (in ribs, ridges, etc.), as suggested at 12 in Fig. 2, increasing the effective heat dissipative surface area and proportionately increasing heat dissipation efficiency.

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Heat Dissipative Chip Carriers

Chip carrier 1, shown in top elevation and side views in Fig. 1, has a bottom layer 3 of solid copper used to remove heat from a not shown integrated circuit, mountable upon chip attachment pad 5. This pad, of predominantly dielectric composition, includes heat conductive paths to the sink layer 3 formed through holes 7 lined by plated conductive material 9 (Fig. 2). If the heat dissipating layer 11 is selectively masked during formation of plated linings 9 it will be profiled (in ribs, ridges, etc.), as suggested at 12 in Fig. 2, increasing the effective heat dissipative surface area and proportionately increasing heat dissipation efficiency.

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