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Dynamically Paged Control Store Buffer Management

IP.com Disclosure Number: IPCOM000077032D
Original Publication Date: 1972-May-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 3 page(s) / 54K

Publishing Venue

IBM

Related People

Kurtz, C: AUTHOR [+3]

Abstract

A number of implementations for managing a dynamically paged control store are disclosed. In the drawing, the micro instructions to be executed from a control store data register 1 are accessed from a large backing store or control data base store, such as main memory 2, into a changeable control store buffer 3. The microprogram module required for instruction execution is accessed from the control data base 2 by a module loader 4, in response to selected machine language instructions 5 obtained in sequence from an instruction buffer 6. The placement of microprogram modules from control data base 2 into the control store buffer 3 is by a fill control 7.

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Dynamically Paged Control Store Buffer Management

A number of implementations for managing a dynamically paged control store are disclosed. In the drawing, the micro instructions to be executed from a control store data register 1 are accessed from a large backing store or control data base store, such as main memory 2, into a changeable control store buffer
3. The microprogram module required for instruction execution is accessed from the control data base 2 by a module loader 4, in response to selected machine language instructions 5 obtained in sequence from an instruction buffer 6. The placement of microprogram modules from control data base 2 into the control store buffer 3 is by a fill control 7. The access of individual micro instructions from a control store buffer 3 into the register 1 is by a read control 8, which responds to requirements of a processing system and the sequence generated by each succeeding micro instruction in the data register 1.

Two parameters of buffer management significantly affecting cost and performance are module placement and fill level detection.

Module Placement - Module in Single Partition - (MISP) - The simplest organization shown at 9 is to divide the buffer address space into (N) equal size partitions, where (N) is the number of microcode modules desired to be pre- paged. Each partition will hold one and only one microcode module. This implies that each partition be at least as large as the largest microcode module.

Module in Multiple Partitions - (MIMP) - A more complex but more efficient organization shown at 10 divides the buffer address space into (N) equal size partitions of (M) words each. The value of (M) is arbitrary but is probably best chosen to be near the mean value of module sizes. The value of (N) would depend upon the total number of words required to provide the desired pre- paging. This organization provides for the occupation of multiple, contiguous partitions by a single microcode module.

Partition List - A further organization shown at 11, divides the buffer 3 into block sizes which would correspond, most efficiently, to the number of micro- instruction words transferred from the control data base 2 to the control store buffer 3 on each access to the control data base 2. This organization provides for the occupation of multiple, contiguous blocks of addresses by each microcode module with the need only to separate each of the microcode modules by one block of addresses.

Buffer Size - Certainly the buffer size required in the MIMP organization (NxM) would be less than that required by the MISP organization (NxLargest Microcode Module). The magnitude of the difference is a function of the microcode profile and the resulting partition sizes required.

Fill Level Detection - A parameter with substantial influence upon the performance seen by a processing element using a dynamically paged control store concept, is the ability to use that portion of a microcode module which ha...