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Interrupt System for a Multiprocessor

IP.com Disclosure Number: IPCOM000077035D
Original Publication Date: 1972-May-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 3 page(s) / 79K

Publishing Venue

IBM

Related People

Albanes, NJ: AUTHOR

Abstract

The figure shows an interrupt system that is designed to function with a plurality of simplex processors arranged as a multiprocessor. The interrupt system is compatible with multiple input/output controllers (IOC,s), central processors (CPU's) and main memories (MM's) of a multiprocessor. The interrupt system makes extensive use of the preferential storage area (PSA) concept.

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Interrupt System for a Multiprocessor

The figure shows an interrupt system that is designed to function with a plurality of simplex processors arranged as a multiprocessor. The interrupt system is compatible with multiple input/output controllers (IOC,s), central processors (CPU's) and main memories (MM's) of a multiprocessor. The interrupt system makes extensive use of the preferential storage area (PSA) concept.

The interrupt system is composed of four subsystems. One subsystem auto stores into (PSA) on any status delta when Masked ON. Another subsystem provides the interrupt signal to the CPU on any status delta since the last test I/O. A third subsystem via a test I/O generated as a part of the CPU interrupt routine, provides storage into a separate PSA location of preprogrammed input/output channel controllers (IOCC) control and status contents prior to clearing the IOCC status thus reported. A fourth subsystem of masking allows masking of the interrupt to the CPU at the CPU, separate from the masking of the auto store to the PSA at the IOC. The mask at the CPU is obtained from a PSA location and loaded by "load-to CPU self" instructions. This mask being in PSA is inspectable or settable by any CPU. The mask at the IOC is obtained in the course of terminal commands to IOCC in accord with the modified IOC baseline.

The interrupt system separates the reporting into main memory MM of the latest status change from the interrupt to the CPU. The system provides facility for inspection of status independent of the interrupt to the CPU.

The IOC status register (Stat Reg) in the figure is set by each of the three IOCC's separately. The IOC Stat Reg is divided into three 10-bit IOCC registers. The satire IOC Stat Reg is stored with any store into MM. The store of the IOC Stat Reg is in two ways:
(1) Auto store on any status change or delta (2) Store on a test I/O.

The auto store on any delta is inhibited during any test I/O. The auto store on the delta is maskable by the IOC on an IOCC basis. The IOCC mask at the IOC is applied or removed in accord with IOC/data bus terminal "A" type commands. The store on a test I/O is maskable by the CPU at the CPU on an IOCC basis. The IOCC mask at the CPU is applied by a CPU instruction.

The auto store on any status delta is on initial MASK ON and thereafter on any delta so long as Masked ON. The auto store on any delta is to a PSA "store stat on delta". This PSA location is assigned for each IOC in each of the CPU's PSA's. The use of auto store into PSA allows any CPU to inspect channel status of all three IOCC's with ons PSA access.

The store on a test I/O is to a PSA designated "test I/O store stat". This PSA location is available once in each of the CPU's PSA's. This PSA is...