Browse Prior Art Database

Ring Interconnection System

IP.com Disclosure Number: IPCOM000077037D
Original Publication Date: 1972-Jun-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 3 page(s) / 45K

Publishing Venue

IBM

Related People

Bliss, BE: AUTHOR [+2]

Abstract

This parallel processing system includes an n-stage ring shifting subsystem for distribution of time division multiplexed message intelligence signals between a total of n processing, memory and input/output units. The latter units are collectively designated as load units L(O),...,L(n). Cross-ring direct connection paths 2 are used to bypass the slower ring shifting path for rapid communications; for example, between processing and memory modules at diametrically opposite positions on the ring in a time-critical memory access operation.

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Ring Interconnection System

This parallel processing system includes an n-stage ring shifting subsystem for distribution of time division multiplexed message intelligence signals between a total of n processing, memory and input/output units. The latter units are collectively designated as load units L(O),...,L(n). Cross-ring direct connection paths 2 are used to bypass the slower ring shifting path for rapid communications; for example, between processing and memory modules at diametrically opposite positions on the ring in a time-critical memory access operation.

Messages may include requests for specific services such as memory fetch operations. Messages are entered into the ring shifting subsystem together with source, destination, and message class identification codes. To enter their messages into the ring, the load units are assigned respective unique time divisions of a basic n-period time frame. the frame time corresponds to the time required for a message to shift once around the ring.

The ring stages S(O),...,S(n) include respective registers with sufficient capacity to hold a message and associated supplemental identification codes. These registers are ring interconnected for parallel shifting.

An eight stage system is specifically illustrated in the accompanying drawing. Ring inputs, shifts, and outputs are controlled by not shown clock timing, gating and condition latching circuits associated with the ring stages. Cross-ring communications are controlled by indicated per-stage groups of condition latches: H, IMT, O/R, O/CR, O/CI, R/CR, CA. More complete descriptions of the functions of these latches follow.

H: Home latch, set by address compare logic associated with preceding ring stage, indicates when set that data

shifting into respective ring stage is destined for IR

(Input Register) in Load Unit of that stage.

IMT: Input Empty latch indicates when set that IR (Input Register) of the respective ring stage is accessible.

O/R: Output/Ring latch signifies...