Browse Prior Art Database

Memory Cell Sense Line Recovery With Schottky Diodes

IP.com Disclosure Number: IPCOM000077042D
Original Publication Date: 1972-Jun-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Platt, S: AUTHOR

Abstract

Each memory cell is a stable capacitive store cell, in which the information is the charge accumulated on a storage node. The integrated Schottky barrier diodes (D1,D2) eliminates the need for additional bit-sense line restore circuitry. Periodic regeneration is required due to leakage across the storage capacitance (a reverse biased PN junction). A high voltage on the storage node is defined as a "1" while a low voltage is defined as a "0".

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Memory Cell Sense Line Recovery With Schottky Diodes

Each memory cell is a stable capacitive store cell, in which the information is the charge accumulated on a storage node. The integrated Schottky barrier diodes (D1,D2) eliminates the need for additional bit-sense line restore circuitry. Periodic regeneration is required due to leakage across the storage capacitance (a reverse biased PN junction). A high voltage on the storage node is defined as a "1" while a low voltage is defined as a "0".

In standby, the write line is low (0 volt) and the read line is high (3 volts). Both the NPN (T1) and the PNP (T2) transistors are off. The bit sense line is biased at V reference (2.6 volts). TL perform a read, the write line is held low (0 volt) while the read line is brought to 0 volt. A stored 1 turns on the NPN T1 transistor, drawing sense current from the bit line. Sense current remains present until the bit line voltage is clamped by the Schottky barrier diode D2 of the nonselected cells common to the bit line.

The Schottky diodes limit the bit line voltage swings to a few hundred millivolts, eliminating sense line recovery through the RC time constant of subcollector underpass to the sense amplifier reference voltage.

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