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General Function Circuit

IP.com Disclosure Number: IPCOM000077043D
Original Publication Date: 1972-Jun-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Machart, DL: AUTHOR [+2]

Abstract

The circuit of Fig. 1. operating with three control lines G1, C2 and G3 generates the Boolean functions shown in the table of Fig. 2. The output cell (cell 3 of Fig. 1) is an "exclusive OR" which permits use of the circuit to implement a half-add capability. Further, two stages of the circuit of Fig. 1 may be utilized to impart increment capability.

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General Function Circuit

The circuit of Fig. 1. operating with three control lines G1, C2 and G3 generates the Boolean functions shown in the table of Fig. 2. The output cell (cell 3 of Fig. 1) is an "exclusive OR" which permits use of the circuit to implement a half-add capability. Further, two stages of the circuit of Fig. 1 may be utilized to impart increment capability.

The embodiment of Fig. 3 illustrates a two variable logic function generator with four control lines, A, B, C and D; which is capable of generating an output based on sixteen different logical combinations.

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