Browse Prior Art Database

Multifunction Logic Circuit

IP.com Disclosure Number: IPCOM000077049D
Original Publication Date: 1972-Jun-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Machart, DL: AUTHOR

Abstract

Circuit 10 performs logic and counting operations upon sequential data from a mask input, and outputs the results at separate terminals RR1, RR2, RR3. Functions such as N-way OR, N-way AND, and M out of N are achieved by pushing 1-bits into successive stages whenever the mask input is a logic 1.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 56% of the total text.

Page 1 of 2

Multifunction Logic Circuit

Circuit 10 performs logic and counting operations upon sequential data from a mask input, and outputs the results at separate terminals RR1, RR2, RR3. Functions such as N-way OR, N-way AND, and M out of N are achieved by pushing 1-bits into successive stages whenever the mask input is a logic 1.

Assuming that all latches 20, 30, 40 are initially reset, any logic 1 signal on mask input 11, which is synchronized with a periodic push signal on line 12, activates AND 21 and OR 22 to set the data input of master-slave latch 20, in conjunction with the leading edge of a clock signal on line 13. The trailing edge of clock signal 13 then produces a signal on latch output 23. Since output 23 enables AND 24, succeeding push signals 12 will maintain output signal 23 regardless of the succeeding states of mask signal 11. Therefore, the signal at output terminal RR1 is a "1 out of N" (i.e., an "OR") function of the mask signals
11.

Any subsequent logic 1 signal at input 11 causes output 23 to be transferred to the data input of master-slave latch 30, via AND 31 and OR 32, when synchronized to push signal 12 and the leading edge of clock signal 13. The next trailing edge of the clock then activates output 33, which maintains itself through AND 34 and OR 32.

Thus the signal at terminal RR2 is a "2 out of N" function of mask signals 11.

Any logic 1 mask signal occurring after latch 30 is set will similarly activate and maintain output 43 of latch 40,...