Browse Prior Art Database

Resist Process

IP.com Disclosure Number: IPCOM000077065D
Original Publication Date: 1972-Jun-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Horst, RS: AUTHOR [+3]

Abstract

Prior to the normal resist patterning process, a sublayer of photo resist is applied to the substrate, blanket-exposed and postbaked to provide a resist system with improved adhesion.

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Resist Process

Prior to the normal resist patterning process, a sublayer of photo resist is applied to the substrate, blanket-exposed and postbaked to provide a resist system with improved adhesion.

A thin layer of a positive photoresist, for example, Shipley AZ-1350* resist, is applied to a silicon semiconductor wafer, prebaked, and then blanket-exposed for about one minute to destroy the sensitizer. The layer is then postbaked for about 30 minutes at a high temperature such as 170 degrees C. A second layer of positive photoresist is then applied on top of the first layer, prebaked, and exposed in a conventional manner to a pattern of radiation. The resist layers are then developed with Shipley AZ* developer. No further postbake is employed so that reflow of the resulting resist pattern is avoided.

The process can also be used with negative resists, in which case there is no prebake of the first layer so that heat induced cross-linking of the first layer is avoided. The process can also employ a combination of resists wherein, for example, the first adhesion promoting layer is a positive resist and the second patterning layer is a negative resist. * Trademark of Shipley Company, Inc.

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