Browse Prior Art Database

Sequence Synchronizer

IP.com Disclosure Number: IPCOM000077072D
Original Publication Date: 1972-Jun-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 5 page(s) / 43K

Publishing Venue

IBM

Related People

King, JH: AUTHOR [+2]

Abstract

A means is provided for reliably synchronizing the transmission and reception of serial digital information even in the presence of errors.

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Sequence Synchronizer

A means is provided for reliably synchronizing the transmission and reception of serial digital information even in the presence of errors.

All digital systems that transmit information must depend upon correct and reliable synchronization. Once a synchronizing sequence of bits has been identified at the receiver, the information bits that follow can be sensed. It is mandatory for correct operation that there is no failure to sync when desired, and also that there is no false sync.

Some typical types of applications for this requirement are in start-stop transmission and reception (decoding) of digital information over any type of information transmission channel, e.g., radio link or telephone line link; bar coded information on discrete documents; etc., where information is transmitted in discrete fields of bits, and where the time separation of the beginning of each field is not precisely controlled.

Syncing on the first 1 bit of the information, or on any single bit, for example, is not adequate; if, due to error, the bit is not sensed, or if a false bit is sensed due to noise, incorrect syncing will result.

Previous work has been aimed at utilizing synchronizing sequence; of bits that have a certain probability of not occurring randomly, or at utilizing self- synchronizing codes for the information, in which continual synchronization is maintained.

The present arrangement specifies particular synchronizing codes that will cause correct synchronization even in the presence of a predetermined number of bit errors.

It should be noted that conventional error correcting codes are not sufficient here. It should also be noted that any error detection or correction coding of the digital information itself can be done conventionally, and is not a part of this problem.

Refer to Figure 1. Following "turn on," or the sensing of some previous information, the system is in "standby," waiting for a synchronizing sequence. Following the satisfactory sensing of this sync sequence, the system is in sync, and the information bits are then transmitted and received. If it were impossible for any failures to occur, a single 1 bit, for example, would be used as the syncing sequence.

However, noise or other failures can cause erroneous 1's to appear during standby, or can cause failures in the syncing sequence. Both cases result in erroneous operation: either failing to sync at the right time, or syncing at the wrong time.

The present arrangement guarantees that even if N bit errors occur during standby and/or the synchronizing sequence, the system will still correctly

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synchronize. The larger N is selected to be, the longer must be the synchronizing code.

A single-error permitting code is 11010. Syncing will correctly occur after any of the following sequences (the underline indicates the position of the single error), and only after these sequences: 1 1 0 1 0

1 1 0 1 1

1 1 0 0 0

1 1 1 1 0

1 0 0 1 0

0 1 0 1 0

1 (0)...