Browse Prior Art Database

Double Frequency Modulation Clock Separator

IP.com Disclosure Number: IPCOM000077081D
Original Publication Date: 1972-Jun-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Grimes, DW: AUTHOR

Abstract

When double-frequency encoded data and clock information is recorded at high density on a magnetic medium, unbalanced forces will exist between magnetized areas on the magnetic medium causing the magnetized areas to physically move or skew towards equilibrium positions. The clock data separator shown in Fig. 1 can correctly separate clock pulses from data, even though a clock pulse may be as much as 240 nanoseconds early or 240 nanoseconds late, and a data pulse may be as much as 170 nanoseconds early or 190 nanoseconds late in a data cell of nominal length 400 nanoseconds between clock pulses. Maximum expected skew is +/-70 nanoseconds for clock pulses and +/-30 nanoseconds for data pulses.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 2

Double Frequency Modulation Clock Separator

When double-frequency encoded data and clock information is recorded at high density on a magnetic medium, unbalanced forces will exist between magnetized areas on the magnetic medium causing the magnetized areas to physically move or skew towards equilibrium positions. The clock data separator shown in Fig. 1 can correctly separate clock pulses from data, even though a clock pulse may be as much as 240 nanoseconds early or 240 nanoseconds late, and a data pulse may be as much as 170 nanoseconds early or 190 nanoseconds late in a data cell of nominal length 400 nanoseconds between clock pulses. Maximum expected skew is +/-70 nanoseconds for clock pulses and +/-30 nanoseconds for data pulses.

Read-head circuit 12 detects and rectifies each magnetization transition and provides an output pulse approximately 100 nanoseconds long for each transition. Inverting time-delay circuit 14 with AND gate 16 operate as a pulse generator to provide a 30 nanosecond pulse for each clock and each data transition, as shown in waveform A of Fig. 2. During the synchronization portion of each frame, only clock transitions are received from read-head circuit 12. The first clock transition enables AND gate 18 having an output waveform B, shown in Fig. 2, which sets timing latch gates 20 and 22. The output of the timing latch is waveform C which is delayed by time delay 24 to generate waveform D, and again delayed by time delay 26 to generate waveform E. Waveforms D and E are connected back to inputs of AND gate 18 to prevent a subsequent data transition from being recognized as a clock transition....