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Multiple Level Interrupt System for Multiprocessor

IP.com Disclosure Number: IPCOM000077082D
Original Publication Date: 1972-Jun-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 3 page(s) / 60K

Publishing Venue

IBM

Related People

Albanes, NJ: AUTHOR

Abstract

A multiple level interrupt system is shown in the figure. The interrupt system makes extensive use of the preferential storage area (PSA). A single-level system generally completes the essential services for one interrupt before returning to the interrupted processing, or before beginning service for another interrupt. This multiple level system provides for the interruption of either "operational" processing or interrupt servicing.

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Multiple Level Interrupt System for Multiprocessor

A multiple level interrupt system is shown in the figure. The interrupt system makes extensive use of the preferential storage area (PSA). A single-level system generally completes the essential services for one interrupt before returning to the interrupted processing, or before beginning service for another interrupt. This multiple level system provides for the interruption of either "operational" processing or interrupt servicing.

The multiple level system incorporates replicated scratch pad memories (SPM's). Replication automatically provides a "SAVE" upon interrupt. Each interrupt level is provided with its own replicated SPM and is pointed to by the SPM select register (SSR).

The processing at one interrupt level continues until a higher level is masked "ON" and requests service. The change from one interrupt level to another occurs at the "interruptability" period.

The sensing of a masked "CN" interrupt during the "interruptability" period causes a transfer from Instruction Fetch to the Interrupt Micro Routine. The Interrupt Micro Routine will then clear and set the SSR and store SSR into the PSA.

The set of the SPM Select Register SSR during the microroutine is preceded in the microcycle by a "clear", effectively allowing any pending "MASKED CN" interrupt signal sources to be entered into the SSR.

The interrupt microroutine upon completion causes transfer to Instruction Fetch. The Program Counter (PC) from SPM is addressed in accord with the SPM Select Address in the SSR. The highest interrupt level is selected.

The servicing of the interrupt level proceeds under an effective "MASK OFF" of any new signal sources of the same or lower interrupt level. Should there occur a higher level interrupt signal the interrupt servicing of the lower level will be interrupted. The presence of a "MASKED ON" higher level interrupt signal source again calls in the interrupt microroutine to clear and set the SSR and to store SSR in PSA. In the case when the lower level interrupt servicing was not completed, then both interrupt level requests will appear in the SSR but only the higher level SPM will be selected.

During the interrupt servicing after the interrupt signal source has been reset or cleared (i.e., having just been serviced) an instruction "Terminate Multiple Interrupt" does as follows: Provides program counter (P.C.) to SPM(pc) to prepare for the next interrupt (for the level just serviced) on exit. P.C. is obtained from main memory (MM) per absolute logical address (Z) of instruction (INSTR). Continues microaction. Transfers to interrupt microroutine to clear then set the SSR and to store SSR in PSA. This microaction provides for the automatic transfer on exit to the highest level interrupt requesting service. Exit from this ...