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Digital Synchronizer

IP.com Disclosure Number: IPCOM000077085D
Original Publication Date: 1972-Jun-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 3 page(s) / 53K

Publishing Venue

IBM

Related People

Galpin, RJ: AUTHOR

Abstract

The problem of detecting a prescribed synchronization bit pattern in a serial pulse code modulated stream of input data, and allowing adjustable tolerance levels on that synchronization bit pattern can be accomplished with either of the above two, all digital circuits. For purposes of example, a 36-bit sync pattern 011010101011010100 101101001101010111 is divided into four segments of nine bits each. The length of the bit pattern and its division into segments is, of course, arbitrary, but for the purpose of this example, each segment of the 36-bit pattern will contain nine bits which can be encoded into the 512 memory addresses of a medium scale integration chip.

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Digital Synchronizer

The problem of detecting a prescribed synchronization bit pattern in a serial pulse code modulated stream of input data, and allowing adjustable tolerance levels on that synchronization bit pattern can be accomplished with either of the above two, all digital circuits. For purposes of example, a 36-bit sync pattern 011010101011010100 101101001101010111 is divided into four segments of nine bits each. The length of the bit pattern and its division into segments is, of course, arbitrary, but for the purpose of this example, each segment of the 36-bit pattern will contain nine bits which can be encoded into the 512 memory addresses of a medium scale integration chip.

Referring to Fig. 1, the 36-bit sync pattern is loaded into register 10, so that the first nine register stages labeled 12 contain the first segment of nine bits and the last nine register stages 18 the fourth segment. In like manner, shift register 20 is divided into four segments so that the first nine shift register stages 22 correspond to segment 1, and the last nine shift register stages 28 correspond to segment 4. As each new bit in a serial pulse code modulated stream of input data is shifted into the last stage of register 20, the contents of each stage of shift register 20 is compared with the contents of each stage of register 10 by the 36 exclusive OR circuits 30. The outputs of the first nine exclusive OR circuits 32 are connected to the nine address inputs of read-only memory 42. In like manner the nine outputs of exclusive OR circuits 34, 36 and 38 are connected to the nine address inputs of read-only memories 44, 46, and 48. The output of each exclusive OR circuit of exclusive OR circuits 30 is a logical zero, if corresponding bits of register 10 and shift register 20 compare, and is a logical one if the corresponding bits of register 10 and shift 20 do not compare. The outputs of the nine exclusive OR circuits 32 generate an address of a memory location within read-only memory 42, which contains a four-bit binary count corresponding to the number of logical one bits (or noncompares) in the address. This four-bit count is provided to adder 50. In like manner, read-only memories 44, 46 and 48 provide four-bit counts corresponding to the number of noncompares represented by one bits in their respective addresses to adder 50, adder 54, and adder 54, respectively. Adder 52 sums the outputs of adder 50 and 54, to generate a binary number equal to the total count of noncompares between the bits...