Browse Prior Art Database

Processor Interrupt Buffer Mechanism

IP.com Disclosure Number: IPCOM000077097D
Original Publication Date: 1972-Jun-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Dodd, PD: AUTHOR [+3]

Abstract

A method is provided for buffering interrupt information 1 in the local storage 2 of a computer.

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Processor Interrupt Buffer Mechanism

A method is provided for buffering interrupt information 1 in the local storage 2 of a computer.

An area in local storage 2 is set aside as an interrupt queue 3. This buffer area is able to contain information concerning as many interrupts as it is desirable to buffer at one time. The interrupt control 4 is responsible for storing interrupt information in a first-in first-out sequence in the queue 3 and informing the CPU of the next interrupt to be processed.

When an interrupt event is detected by interrupt control 4, the following sequence of actions takes place. The queue pointer 5 (address of the last interrupt information placed in the queue) is compared with the post pointer 6 (address of the last interrupt information signaled to the CPU). If the post pointer 6 is one larger than the queue pointer 5 (modulo the size of the queue), the queue is full, and the interrupt queue overflow latch 7 is set. Otherwise, the queue pointer 5 is incremented by one (modulo the size of the queue) and used as the address to store the interrupt information 1. This completes the interrupt queue sequence.

When the interrupt pending latch 8 is off, the following sequence of events takes place. The post pointer 6 is compared with the queue pointer 5. If they are equal, the queue is empty and no action is taken. Otherwise, the post pointer is incremented by one (modulo the size of the buffer) and stored at the post address 9, also within local...