Browse Prior Art Database

Synchronized Analog Burst Gate

IP.com Disclosure Number: IPCOM000077101D
Original Publication Date: 1972-Jun-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Krumins, A: AUTHOR [+2]

Abstract

This analog burst gate accurately begins and ends the burst output on the identical portion of an AC carrier input signal, and also provides a separate synchronizing output in time coincidence with the beginning and ending of the burst output.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 87% of the total text.

Page 1 of 2

Synchronized Analog Burst Gate

This analog burst gate accurately begins and ends the burst output on the identical portion of an AC carrier input signal, and also provides a separate synchronizing output in time coincidence with the beginning and ending of the burst output.

A carrier signal input 10, which may take a variety of forms, for example, a constant frequency/constant amplitude signal or a variable frequency/variable amplitude signal, is applied as an input to analog switch 11 and comparator 12. The comparator detects a selected portion of the carrier, for example the positive-going zero-crossing, and enables single-shot 13 when this portion is detected. Output 14 of the single-shot is active for a short time interval of 30 nanoseconds after this zero-crossing of the carrier is detected. A coincidence of output 14 and a control gate input 15 sets latch 16, causing its output 17 to become active. The active output of latch 16 enables switch 11 by way of conductor 18.

Carrier 10, and specifically the selected zero-crossing, now appears at output 19 as the beginning of the burst output. Output 19 continues thereafter to correspond to input 10, until such time as gate input 15 becomes inactive. Thereafter, the first positive-going zero-crossing of the carrier is operable to reset latch 16. The output of the latch now becomes inactive, and switch 11 is inhibited.

The end of the burst output occurs at this zero-crossing. Thereby only full cycles of the carrier...