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Automatic Zero Correction Amplifier

IP.com Disclosure Number: IPCOM000077115D
Original Publication Date: 1972-Jun-01
Included in the Prior Art Database: 2005-Feb-24
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Hellwarth, GA: AUTHOR [+3]

Abstract

Automatic zero correction for cascade connected amplifiers 1 and 2 is provided by the circuit of Fig. 1. Operation occurs in a two-phase sequence. Operation begins with the error-storage phase by opening switches 3 and 4 and closing switches 5, 6, and 7. During this period the offset voltage of amplifier 1 and 2 is stored by the sample and hold circuit comprising capacitor 8 and amplifier 9. The amplification phase begins with the opening of switches 5, 6 and 7 and closing of switches 3 and 4, permitting normal amplification of the unknown voltage V1 and V2. The correction voltage stored on capacitor 8 is also applied to an input of amplifier 1 in a fashion to oppose the offset or error voltage induced by amplifier 1, 2 or 9.

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Automatic Zero Correction Amplifier

Automatic zero correction for cascade connected amplifiers 1 and 2 is provided by the circuit of Fig. 1. Operation occurs in a two-phase sequence. Operation begins with the error-storage phase by opening switches 3 and 4 and closing switches 5, 6, and 7. During this period the offset voltage of amplifier 1 and 2 is stored by the sample and hold circuit comprising capacitor 8 and amplifier 9. The amplification phase begins with the opening of switches 5, 6 and 7 and closing of switches 3 and 4, permitting normal amplification of the unknown voltage V1 and V2. The correction voltage stored on capacitor 8 is also applied to an input of amplifier 1 in a fashion to oppose the offset or error voltage induced by amplifier 1, 2 or 9.

Resistor 12 is equal to the source resistance of networks 10 and 11, so that amplifier 1 sees the same resistance when switch 4 is closed as that seen when switch 6 is closed. Resistor 30 provides similar compensation for the other input to amplifier 1.

Application of the correction voltage to an amplifier input after the first stage allows a relatively large-error voltage to be stored by the sample and hold circuitry. This has the effect of reducing the error caused by sample and hold inaccuracies. A similar effect could be obtained by placing an attenuator in the output of the sample and hold circuit and connecting the attenuated correction signal to the appropriate input of amplifier 1.

An implementatio...