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Browse Prior Art Database

Latch Circuit

IP.com Disclosure Number: IPCOM000077153D
Original Publication Date: 1972-Jun-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Hart, RL: AUTHOR [+2]

Abstract

This latch circuit eliminates both false output and skewing of binary output signals on latch output terminal 42, by ensuring that no delay occurs between the application of signals on clock 1 line 22 and clock 2 line 24 to set AND gate 26 and hold-clear AND gate 28, respectively. Moreover, override logic AND gate 30, which is responsive to binary signals on data set line 20, ensures that the correct binary state is maintained at terminal 42 during simultaneous conditioning of gates 26 and 28 by clock signal transitions from one binary state to another.

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Latch Circuit

This latch circuit eliminates both false output and skewing of binary output signals on latch output terminal 42, by ensuring that no delay occurs between the application of signals on clock 1 line 22 and clock 2 line 24 to set AND gate 26 and hold-clear AND gate 28, respectively. Moreover, override logic AND gate 30, which is responsive to binary signals on data set line 20, ensures that the correct binary state is maintained at terminal 42 during simultaneous conditioning of gates 26 and 28 by clock signal transitions from one binary state to another.

Assuming a binary 1 is to be written into the latch and that terminal 42 is already in a binary 1 state, then the binary 1 on line 20 in conjunction with the binary 1 state of the clock 1 signal set terminal 42 to a binary 1 via input terminals 32 and 36 of gate 26.

At the same time, the clock 2 signal on line 24 clears terminal 42 of any previous information, since terminal 38 momentarily disables gate 28.

During the enabling of gate 26 and the enabling of gate 28, gate 30 ensures that terminal 42 is maintained at the binary state in which the latch is being set, for those cases in which the latch goes from a 1 to a 1 state. With terminal 42 in a binary 1 state, a binary 1 is applied to both terminals 44 and 46 by feedback from terminal 40. Upon-applying a binary 1 to line 20 and terminal 34, and with a binary 1 on terminal 46, gate 30 is gated to maintain a binary 1 on output terminal 42 during con...