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Field Effect Transistor Decoder

IP.com Disclosure Number: IPCOM000077177D
Original Publication Date: 1972-Jun-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 3 page(s) / 25K

Publishing Venue

IBM

Related People

Baitinger, U: AUTHOR [+3]

Abstract

The unit involved is a field-effect transistor (FET) decoder operating at extremely high speed, its function being the addressing of monolithic FET storages.

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Field Effect Transistor Decoder

The unit involved is a field-effect transistor (FET) decoder operating at extremely high speed, its function being the addressing of monolithic FET storages.

The output circuit of the decoder consists of an FET T5, a capacity C being connected between its gate and source.

In a selected decoder, capacity C and thus node Vc are charged and T5 is conductive. A selection pulse applied to connection P of the drain is transmitted to output A via T5.

In a nonselected decoder, capacity C and thus node Vc are discharged and T5 is nonconductive. The selection pulse is not transmitted.

In the quiescent state, capacity C is maintained in the charged state via a FET T4 connected to node Vc, the gate of FET T4 receiving a restore pulse via connection R.

The addressing of the decoder is performed via input FET's T1 - T3 connected to node Vc. The number of these FET's depends on the respective decoding. Upon the addressing of the storage capacities, C of all nonselected decoders are discharged by at least one of input FET's T1 - T3 becoming conductive. In a selected decoder, C remains charged owing to the fact that all input FET's T1 - T3 remain nonconductive. As soon as capacities C of all nonselected decoders are discharged, the selection pulse can be applied to connections P. The decoder speed desired is achieved as follows:

Depending on the personalization of the decoders, the gates and sources of the input FET's T1, T2, and T3 are connected to the outputs E1, E2, and E3 of address buffers, or to the outputs E1, E2, and E3 of address inverte...