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Computer Assisted System Test of Peripheral Device Attachment

IP.com Disclosure Number: IPCOM000077202D
Original Publication Date: 1972-Jun-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Hallmark, JA: AUTHOR [+2]

Abstract

Rapid testing of peripheral devices is accomplished with an adapter, which permits easy compression of data received from the device with data generated by the Central Processing Unit which controls the adapter. The CPU 1 is connected to the peripheral device 2 under test through a test adapter unit 3. An output register 4 and an input register 5, contained in the adapter unit 3, provide an interface between CPU 1 and the peripheral device 2.

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Computer Assisted System Test of Peripheral Device Attachment

Rapid testing of peripheral devices is accomplished with an adapter, which permits easy compression of data received from the device with data generated by the Central Processing Unit which controls the adapter. The CPU 1 is connected to the peripheral device 2 under test through a test adapter unit 3. An output register 4 and an input register 5, contained in the adapter unit 3, provide an interface between CPU 1 and the peripheral device 2.

Each of registers 4 and 5 is divided into 2 portions. In the case of register 4, one portion is connected to peripheral device 2 and the other portion leads to wrap cable 6. Register 5 has one portion converted to receive an input from peripheral device 2 and the other portion connected to wrap cable 6. With this hardware configuration, it is possible for CPU 1 to load register 4 with data by a single instruction. The data in the portion of register 4 connected to device 2 represents a command to device 2.

The response of device 2 in executing the command is transmitted to register 5 with the data in register 5 then being transmitted back to CPU 1. The performance of device 2 may then be evaluated by making a logical comparison with a programmed expected response. Verification of the adapter hardware without disturbing the interface connections between device 2 and registers 4 and 5 is possible, by CPU 1 writing into cable 6 from register 4 and sensing register 5....