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Method for cross-link debugging using event sharing between repeaters and buffers in high-speed serial links

IP.com Disclosure Number: IPCOM000077216D
Publication Date: 2005-Feb-25
Document File: 7 page(s) / 192K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for cross-link debugging using event sharing between repeaters and buffers in high-speed serial links. Benefits include improved debug/validation tools functionality, and performance, using a low cost cross triggering scheme.

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Method for cross-link debugging using event sharing between repeaters and buffers in high-speed serial links

Disclosed is a method for cross-link debugging using event sharing between repeaters and buffers in high-speed serial links. Benefits include improved debug/validation tools functionality, and performance, using a low cost cross triggering scheme.

Background

              Due to the high speed of the memory links and other system interconnects, direct probing is difficult. As a result, buffers and repeaters are implemented to demultiplex (slow down) the traffic to a speed compatible with available logic analyzers. Pass-through devices on these high speed links can be equipped/extended with logic analyzer capabilities such as pattern recognitions to monitor link data transfer activities and to generate decoded and other derived useful debug information.

              Modern computer system architectures require complex buses/links, and are dependent on configurations with several links of the same type working together.  Observability of several bus/links simultaneously is required to expose control and data content in order to debug complex traffic in such systems. In such complex systems it is often necessary to detect sequences of related events occurring in particular orders on different buses/links in the system  (for example: requests followed by simple or complex responses).

              Conventionally, the propagation of detected debug events (selected decodes of monitored bus traffic) through logic analyzers is very slow (on the order of 100s of nanoseconds). A lower latency solution is required for emerging high speed links since related interesting events on the links occur at shorter intervals so that sequences of events can not be readily detected with latencies this long. Additionally, related events detected by logic analyzers can not be made available in time to devices handling the link traffic to allow arming for detection of many interesting sequences of events on the link in order to trigger trace capture to support logic analysis required for debugging or optimizing complex networks.

              Validation and test environments require specialized mechanisms to overcome normal LA tool events latencies to achieve needed cross triggering performance.  Reduced latency can be provided by tools such as the event bus mechanism defined in this paper. This mechanism  enhances test and debug coverage by enabling detection of much more closely timed sequences of events distributed on the multiple busses/links than would be possible using only conventional trigger sharing by logic analyzers.

              The inability to detect complex and rapidly occurring sequences of events on system buses/links can seriously impact ability to fix bugs early and quickly, and can have the following effects:

•             Delay necessary respin steppings devices as problem debug stretches out

·        More test equipment required since each set of equipmen...