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Amplifier Offset Voltage Correction Circuit

IP.com Disclosure Number: IPCOM000077218D
Publication Date: 2005-Feb-25
Document File: 4 page(s) / 300K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a circuit that removes and corrects for inherent offset voltages. In addition, the disclosed method can introduce a known offset increment into the circuit (either large or small), or a known actual offset once the offset correction is determined. Benefits include a solution that does not require additional devices or processing.

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Amplifier Offset Voltage Correction Circuit

Disclosed is a method for a circuit that removes and corrects for inherent offset voltages. In addition, the disclosed method can introduce a known offset increment into the circuit (either large or small), or a known actual offset once the offset correction is determined. Benefits include a solution that does not require additional devices or processing.

Background

Amplifiers in integrated circuits take advantage of the relative matching of devices to improve performance. Imperfections in the fabrication process lead to inherent mismatches in the devices, leading to input-referred offset voltages. Even though special techniques are used in circuit designs and layouts to reduce these offsets, they are always present. In some cases, improved circuit performance is tied directly to the reduction of the input offset voltage.

In some circuits, a fixed and known offset voltage is desirable. For example, window comparators and threshold detectors determine if a signal is above a voltage threshold. In other applications, the initial offset voltage may be unknown, but a known offset voltage increment is desirable during system operations.

There are several known methods for adjusting the offset voltage:

§         Trimming the wafer at sort

§         Using chopper stabilization or other ping-pong techniques

§         Floating gate structures that modify the threshold voltages of the input devices

§         Auto-zeroing techniques that use a capacitive storage

General Description

The disclosed method relates directly to circuits with differential input device pairs. Most inputs for such circuits consist of matched devices with a tail current source, as shown in the left half of Figure 1.  In the disclosed method, degeneration elements are used in the source connection, and tail currents are injected at various points in the degeneration resistor string. These tail currents are directed to different points in the degeneration string, using an analog multiplexer or switch array.  The right half of Figure 1 shows the disclosed method where one tail current is employed.

Figure 2 shows one circuit embodiment of the disclosed method. With the switch in the middle position, the circuit is balanced, and the extra circuitry adds no extra offset correction voltage. However, when the switch is mov...