Browse Prior Art Database

Extended Front Side Bus Programming Capability

IP.com Disclosure Number: IPCOM000077221D
Publication Date: 2005-Feb-25
Document File: 2 page(s) / 59K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that provides the CPU's front side bus configuration registers with more "tuning" data, to allow more system information and capability programming. Benefits include extending the number of programming bits that can be sent to the CPU.

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Extended Front Side Bus Programming Capability

Disclosed is a method that provides the CPU’s front side bus configuration registers with more “tuning” data, to allow more system information and capability programming. Benefits include extending the number of programming bits that can be sent to the CPU.

Background

Newer processors have many new features and capabilities. This requires more information about the system, and for best characteristics to be programmed into the FSB configuration registers of the Memory controller (MCH) and CPU (see Figure 1). Current methods read pre-programmed data from known places in non-volatile memories, such as the BIOS.  Sub-blocks within the MCH can request that data be read from the BIOS transferred to the MCH configuration registers. Also, a scheme exists where data is passed to the CPU from the MCH, via the host address lines (HADDR). Currently, data is transferred on the address lines at the de-asserting edge of CPU reset (CPURST# - see Figure 2). 

General Description

The disclosed method allows for a second (and third, and so forth) set of data to be sent to the address lines after a pre-determined amount of time, then held for another pre-determined amount of time. The CPU simply times off the edge of the CPURST# to place a second load
(i.e. latch2) to capture the second data set. This approach enables the disclosed method to be extended to more data sets. 

This scheme requires no handshakes, and is simply timing based. The...