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Quadrature-Based Clock-Doubling Circuit

IP.com Disclosure Number: IPCOM000077224D
Publication Date: 2005-Feb-25
Document File: 3 page(s) / 156K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is an RCCR-based method for doubling the clock frequency of a high-speed differential clock. Benefits include achieving the highest possible speed from the PLL structure and enabling easier clock quadrupling and higher multiples.

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Quadrature-Based Clock-Doubling Circuit

Disclosed is an RCCR-based method for doubling the clock frequency of a high-speed differential clock. Benefits include achieving the highest possible speed from the PLL structure and enabling easier clock quadrupling and higher multiples.

Background

Low-jitter high-speed clocks are critical to the performance of serial-data interfaces. With the increasing signaling rates and clock speeds of interfaces, it is becoming increasingly difficult to implement these clocks using traditional PLL and DLL methods. Some high-speed digital circuits have clocking frequencies limited primarily by the PLL’s maximum frequency.

General Description

The disclosed method generates quadrature differential clocks using an RCCR-based structure, then feeds these clocks into a balanced logic structure to generate the double-frequency clock (see Figure 1). A typical two-stage RCCR network is shown in Figure 2.

This network takes as input a differential clock (i.e., ClkinA and ClkinB) along with a Vbias which is the average value of the differential inputs. Each differential input feeds into an RC low-pass filter and a CR high-pass filter. The transfer functions of these two filters are such that at the corner frequency, f = 1/(2 pi R C), the output magnitudes are equal and the phase difference is exactly 90 degrees. At other frequencies the magnitudes are not equal, but the phase difference is still exactly 90 degrees. Furthermore, with the equal output loading of the two filters the phase difference is still exactly 90 degrees. The elements are passive and easily matched in silicon using analog layout techniques; mismatches result in magnitude and phase difference errors. Each stage decreases the output magnitude by approximately six dB, but more importantly, each stage...