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Validating Arbitration Logic in Memory Controllers

IP.com Disclosure Number: IPCOM000077229D
Publication Date: 2005-Feb-25
Document File: 4 page(s) / 383K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for validating memory controller arbitration algorithms. Benefits include a solution that is automated, reduces test development time, and enables faster validation.

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Validating Arbitration Logic in Memory Controllers

Disclosed is a method for validating memory controller arbitration algorithms. Benefits include a solution that is automated, reduces test development time, and enables faster validation.

Background

In computing systems, it is common for resources to be shared among multiple devices or channels. For example, a DMA controller typically has a number of DMA channels to allow programmers to setup multiple DMA requests at once. However, because there is only one memory bus, only one DMA transfer can be active at a time. If multiple requests are pending, the DMA controller selects the next request as determined by an arbitration scheme. Arbitration is the process of selecting between multiple requests to a shared resource. Common arbitration schemes include priority (i.e. where one request channel gets priority over the others) and round-robin (i.e. where each request channel gets equal access). The unit that oversees the arbitration process and selects the next request is known as the arbiter. Arbitration is very common in a number of different components, including the operating system (e.g. process scheduler) and peripheral buses (e.g. PCI).

General Description

Validating arbitration logic requires determining the order that data requests are actually processed by the arbitration unit, then verifying that it matches the expected result. For example, in a round robin implementation, when multiple requests are pending the arbiter accesses each channel in such a way that all pending requests are handled before one channel gets serviced twice. In a priority based design, one or more channels are serviced more frequently than the other channels.

There are three different cases that must be validated: when arbitrating between multiple channels for reading data, writing data, and for both read and write requests (see Figure 1). The disclosed method determines the arbitration order by reading/writing shared data to/from  memory. The resulting memory contents are examined to determine the exact order in which the memory requests were handled. The following are the three cases needing validation:

┬ž         Read arbitration. In the case of read arbitration, all data channels are set up to perform multiple reads from the memory unit. The reads are set up so that they occur simultaneously. An output data buffer is shared among the different read channels. When a data value comes back from the memory controller, it is stored in the next available slot of the data buffer. There is no arbitration for the output buffer, because only one data value is read on the input s...