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Junction Gate Insulated Gate PNP NPN FET Memory Cell with Nondestructive Read Out

IP.com Disclosure Number: IPCOM000077270D
Original Publication Date: 1972-Jul-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Malaviya, SD: AUTHOR

Abstract

The memory cell shown acts as an N-channel FET to store the data but as a junction gate P-channel FET to provide DC sense currents during read out, without destroying stored data. The circuit operates as follows: 1) Write Cycle.

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Junction Gate Insulated Gate PNP NPN FET Memory Cell with Nondestructive Read Out

The memory cell shown acts as an N-channel FET to store the data but as a junction gate P-channel FET to provide DC sense currents during read out, without destroying stored data. The circuit operates as follows: 1) Write Cycle.

The data to be stored is transferred from drain 1 to source 3 by turning CN gate 2 of the N-channel FET. The gate is turned OFF at the end of the "write" cycle and the data is stored in the cell as electrical charge in the capacitance of diffusion 3. 2) Read Cycle.

The read word line 4 is raised to supply DC current through the P-epi to the read bit line 5. The use of the p-epi itself as a read bit line 5 makes the cell compact and facilitates wiring.

If the data stored is "1", the region between diffusion 3 and the subcollector 6 is pinched OFF and very little DC current is available at the read bit line 5. However, if the data stored is "0", the region is not pinched OFF and a large DC current is available in the read bit line. Diffusion 3 acts as the junction gate of a p-channel FET whose drain and source are the read word/bit lines. The read operation does not destroy the stored data. The subcollector 6 ensures complete pinch OFF of the channel even with relatively weak "1" data, thereby improving the worst case "read" current.

By making contact 7 of the read word line of the Schottky-Barrier type (rectifying), interaction between the active and nonactiv...