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Reach Through Mode Operation of Single Electrode Double Threshold Charge Coupled Memory Cell

IP.com Disclosure Number: IPCOM000077281D
Original Publication Date: 1972-Jul-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Ho, IT: AUTHOR [+2]

Abstract

A single-electrode double-threshold charge-coupled random-access memory cell shown in Fig. 1 can operate in a reach-through mode. The p+ diffusions are utilized as word lines while the orthogonal metal lines are bit/sense lines. The two regions which have different threshold voltages are region I, the metal-oxide silicon (MOS) capacitor storage region, and region II, the channel region. In the illustration, a p-channel configuration is assumed with (Image Omitted) where V(r) is the resting voltage of the bit/sense line. This voltage is required to maintain the MOS capacitors at all times. The two different threshold voltages are made possible, in the illustration, by different oxide thicknesses. Other means are available to facilitate the different threshold voltages.

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Reach Through Mode Operation of Single Electrode Double Threshold Charge Coupled Memory Cell

A single-electrode double-threshold charge-coupled random-access memory cell shown in Fig. 1 can operate in a reach-through mode. The p+ diffusions are utilized as word lines while the orthogonal metal lines are bit/sense lines. The two regions which have different threshold voltages are region I, the metal-oxide silicon (MOS) capacitor storage region, and region II, the channel region. In the illustration, a p-channel configuration is assumed with

(Image Omitted)

where V(r) is the resting voltage of the bit/sense line. This voltage is required to maintain the MOS capacitors at all times. The two different threshold voltages are made possible, in the illustration, by different oxide thicknesses. Other means are available to facilitate the different threshold voltages. A thin nitride layer is shown in the drawing but it may be eliminated, if so desired.

A reach-through mode of operation is shown in Fig. 2. When writing "0", only a negligible amount of minority carriers can get into the MOS capacitor region I. Certain quantity of minority carriers will get into the capacitor when writing a "1". In reading, a large negative voltage -V(a) is applied to the word line. This voltage has an amplitude which is larger than the breakdown voltage, or reach-through voltage, V(RT), of the channel region II:

(Image Omitted)

Minority carriers which represent a stored information "1" are...