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Digital Noise Filter Circuit

IP.com Disclosure Number: IPCOM000077291D
Original Publication Date: 1972-Jul-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Cummings, KD: AUTHOR

Abstract

This circuit accomplishes logical filtering of a noisy signal and at the same time also synchronizes the signals to the system clock. The filter comprises a signal phase splitter 10, a reference cell 12, n cells 1 . . . n and a final output cell 14. Each of the n cells comprises two AND circuits 16, 18 and one RS trigger 20. The number of cells n is determined by the noise environment and the requirements for real-time information.

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Digital Noise Filter Circuit

This circuit accomplishes logical filtering of a noisy signal and at the same time also synchronizes the signals to the system clock. The filter comprises a signal phase splitter 10, a reference cell 12, n cells 1 . . . n and a final output cell 14. Each of the n cells comprises two AND circuits 16, 18 and one RS trigger 20. The number of cells n is determined by the noise environment and the requirements for real-time information.

The system clock is utilized to continuously sample the input signal and the signal is clocked into reference cell 12 at the first sample time t1. At sample time t2 the signal is shifted into cell 1 and a new sample is taken at the reference cell. If the level from the reference cell and cell 1 are the same, the set or reset line for cell 3 will become a logical one, whereas, if the output levels from the reference cell and cell 1 are not the same, logical zeros are presented to the set/reset lines of cell 2 and cell 2 does not change state at sample time t3. In general, all previous cells must have the same level before the following cell can assume that level. The equations for the set/reset lines for the nth cell are:

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If the conditions for these equations are fulfilled, then the next sample time will cause cell n to assume the same level as previous cells. If the nth cell is the output cell, then the output trigger 14 assumes the same level and this level is provided to the system as the...