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Memory Cell Using a Single Josephson Tunneling Gate

IP.com Disclosure Number: IPCOM000077302D
Original Publication Date: 1972-Jul-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 3 page(s) / 48K

Publishing Venue

IBM

Related People

Anacker, W: AUTHOR

Abstract

Fig. 1 shows the memory cell in which a write gate 10 is located in a superconducting loop generally designated 12, having portions 12A and 12B. The loop is provided with a first superconducting leg 14A and the second superconducting leg 14B. Located over the write gate is a control line 16, current through which establishes magnetic fields in write gate 10 to change the threshold of gate 10. Located beneath loop 12 is a sense gate 18 which is also a Josephson tunneling gate. The self-inductance L of loop 12 is the same for both parallel paths 12A, 12B connecting leg 14A to leg 14B. This means that currents I(W) or I'(W) will split into equal parts in each portion of loop 12.

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Memory Cell Using a Single Josephson Tunneling Gate

Fig. 1 shows the memory cell in which a write gate 10 is located in a superconducting loop generally designated 12, having portions 12A and 12B. The loop is provided with a first superconducting leg 14A and the second superconducting leg 14B. Located over the write gate is a control line 16, current through which establishes magnetic fields in write gate 10 to change the threshold of gate 10. Located beneath loop 12 is a sense gate 18 which is also a Josephson tunneling gate. The self-inductance L of loop 12 is the same for both parallel paths 12A, 12B connecting leg 14A to leg 14B. This means that currents I(W) or I'(W) will split into equal parts in each portion of loop 12.

The state of the memory cell is determined by the direction of the persistent current in loop 12. In operation, a persistent current is established in loop 12, after which currents flow in control line 16, and into either leg 14A or leg 14B. The current in these legs combines with the persistent current in loop 12. Depending upon the magnitude of the combined current in loop 12, the sense gate 18 will have its voltage state switched.

Fig. 2 schematically illustrates the write operation, clear operation, and read operation for the memory cell. Fig. 3 shows the sequence of applied pulses to achieve these operations.

Referring in more detail to Figs. 2 and 3, the clear operation will be explained. In the top row of Fig. 2, a persistent current flows in a clockwise direction through loop 12. If a current I'(W) is then brought into cell 12 via leg 14B, this will combine with persistent current in loop 12 to provide a large current component flowing in portion 12B of loop 12. In this case, the write gate 10 is not switched to its voltage state. Even if current I'(B) flows in control fine 16, write gate 10 will not switch since the magnitude of current through is small. This means that a clockwise circulating current representing a zero state will always be established in loop 12, independent of the state prior to application of current I'(W) and I'(B). This is the cleared state of the cell.

Referring to row 2 of Fig. 2, a persistent curre...