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MNOS Memory Array Fabricated on an Insulating Substrate

IP.com Disclosure Number: IPCOM000077313D
Original Publication Date: 1972-Jul-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Krick, PJ: AUTHOR

Abstract

The array structure and fabrication procedure described hereinbelow provides a metal nitride-oxide semiconductor (MNOS) memory chip with on-chip decoding. The substrate for the MNOS array consists of a silicon comb structure 1, as shown in Fig. 1, fabricated on an insulating substrate of sapphire or spinel, not shown. The teeth of comb 1 form bit lines 2, the structure of which is shown in greater detail in Figs. 2,3. Each bit line 2 consists of a strip of lightly doped p-type silicon 3 (n-channel devices) with two n+ diffusions 4 formed on each side of p regions 3. Since silicon is etched away between bit lines 2, it is not necessary to use thick oxide to prevent parasitic action between devices.

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MNOS Memory Array Fabricated on an Insulating Substrate

The array structure and fabrication procedure described hereinbelow provides a metal nitride-oxide semiconductor (MNOS) memory chip with on-chip decoding. The substrate for the MNOS array consists of a silicon comb structure 1, as shown in Fig. 1, fabricated on an insulating substrate of sapphire or spinel, not shown. The teeth of comb 1 form bit lines 2, the structure of which is shown in greater detail in Figs. 2,3. Each bit line 2 consists of a strip of lightly doped p- type silicon 3 (n-channel devices) with two n+ diffusions 4 formed on each side of p regions 3. Since silicon is etched away between bit lines 2, it is not necessary to use thick oxide to prevent parasitic action between devices. A composite layer 5 consisting of thin oxide (20 angstroms) and covered with a silicon nitride layer exists everywhere on silicon array substrate 1. As a result, an MNOS device is formed wherever a metal word line 6 and a silicon bit line 2 intersect, as is shown in Fig. 2.

Fabrication steps for MNOS on an insulating substrate (n-channel Devices):
1) Start with a spinel or sapphire wafer with 1 or 2 mu lightly

p-doped silicon.
2) Dope n+ Legions (1st Mask Step).
3) Etch the excess silicon (2nd Mask Step).
4) Grow thick oxide (300 angstroms) for fixed threshold decode

devices,

not shown.
5) Etch oxide from the MNOS array (variable-threshold devices)

(3rd Mask Step - noncritical).
6) Grow 20 angstroms oxide for vari...