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Integrated Al(x)Ga(1-x)As Light Emitting PNPN Memory Cell

IP.com Disclosure Number: IPCOM000077315D
Original Publication Date: 1972-Jul-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Blum, JM: AUTHOR [+2]

Abstract

Arrays of Al(x)Ga(1-x)As light-emitting devices having pnpn four-layer structures exhibiting negative resistance are realized by liquid phase epitaxy processes. In Fig. 1, a p-type Al(x)Ga(1-x)As layer 8, about 10-30 microns thick, is grown on a p-type or semi-insulating GaAs substrate. An n-type impurity, together with Al, is added to the solution during growth to provide a 5 micron thick n-type Al(x)Ga(1-x)As layer 10 having increased aluminum concentration.

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Integrated Al(x)Ga(1-x)As Light Emitting PNPN Memory Cell

Arrays of Al(x)Ga(1-x)As light-emitting devices having pnpn four-layer structures exhibiting negative resistance are realized by liquid phase epitaxy processes. In Fig. 1, a p-type Al(x)Ga(1-x)As layer 8, about 10-30 microns thick, is grown on a p-type or semi-insulating GaAs substrate. An n-type impurity, together with Al, is added to the solution during growth to provide a 5 micron thick n-type Al(x)Ga(1-x)As layer 10 having increased aluminum concentration.

An oxide mask is then deposited and a diffusion pattern is delineated by etching portions of the oxide mask. The etching insures that only the subsequent light-emitting areas of each device will be covered with the masking material. P- type diffusions 12 are then performed to a depth in excess of 5 microns to form isolated n-type areas (Fig. 2). Another layer of oxide 14 is then deposited and holes are etched in the oxide, such that the center part of each light-emitting n- type region is exposed. Further, Al(x)Ga(1-x)As p-type and n-type layers 16, 18 are then grown in these openings to form the pnpn cells.

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