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Bucket Brigade Circuits

IP.com Disclosure Number: IPCOM000077317D
Original Publication Date: 1972-Jul-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 4 page(s) / 50K

Publishing Venue

IBM

Related People

Johnson, CF: AUTHOR

Abstract

Several circuits using "bucket-brigade" philosophy are described. For background, see the article entitled "Bucket Brigade Electronics", IEEE Journal of Solid State Circuits Vol SC-4, Number 3, June 1969, pp 131-136. Difference Signal Storage.

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Bucket Brigade Circuits

Several circuits using "bucket-brigade" philosophy are described. For background, see the article entitled "Bucket Brigade Electronics", IEEE Journal of Solid State Circuits Vol SC-4, Number 3, June 1969, pp 131-136. Difference Signal Storage.

The bucket brigade delay line is similar to a metal-oxide semiconductor shift register, except that samples of analog waveforms are stored in the delay lime rather than logical one's and zero's. The delay line thus allows the storage of speech or other waveforms without the need for analog-to-digital conversion. Conventional operation of the bucket brigade is described with reference to Figs. 1 and 2 which show the input stage of a bipolar delay line. Step A (Fig. 1).

With T gated off, C1 is charged to e1, a voltage representing a sample of the input waveform and C2 is charged to e2, a negative clock voltage. Step B (Fig.
2).

When e3, a positive clock voltage, is applied to the base of the transistor C1 is clamped to e3 and C2 discharges to e2-(e3-e1) if C1 and C2 are equal. Furthermore, if e2 equals e3 in magnitude, then the voltage at C2 is e1. Hence, the input sample voltage has been transferred from C1 to C2. The following stages operate in the same manner in response to clock signals.

Successive samples are thus moved down a chain of stages similar to that shown, resulting in storage of the sampled waveshape.

A technique for storing the difference between two successive waveform samples rather than the samples themselves is proposed. Advantages are: a) Required dynamic range of delay line circuitry is reduced resulting in reduced clock voltages, etc. b) Errors due to storage capacitor discharge are less in absolute value, since stored voltages are smaller.

Difference signal storage requires a modification in the input stage only; the stages operate as previously described. Step A (Fig. 1).

With T gated off, C2 is charged to e2 where e2=R-S1. R is a negative clock voltage and S1 is the first waveform sample. C1 is charged to e1 where e1=S2, the second waveform sample in time. Step B (Fig. 2).

When e3, a positive clock voltage of magnitude R, is applied, C2 discharges to e2-(e3-e1). e2-(e3-e1)=(R-S1)-(R-S2)=S2-S1.

Hence, the difference between sample 2 and sample 1 is stored in C2. Successive differences are formed and moved down the delay line in response to clock voltages. The quantity R-S1 is the output of a difference amplifier using either operational amplifier or conventional circuitry techniques.

Reconstruction of the signal waveform requires adding the difference signals and also can be done using the circuit shown in Figs. 1 and 2 letting:

1

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e2=R+D1 R is a negative clock

D1 is the first difference e1=D2 D2 is the second difference e3=R R is a positive clock output = e2-(e3-e1) = D1 + D2.

D1 + D2 is shifted to a storage capacitor for output. This operation is repeated as successive differences signals appear at the output. Speech Compression.

Bu...