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Dynamic Cell for Leakage Current Measurement

IP.com Disclosure Number: IPCOM000077321D
Original Publication Date: 1972-Jul-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Evrenidis, P: AUTHOR [+2]

Abstract

This described is a test instrument useful in determining the quality of the source-substrate junction in a field-effect transistor (FET). As indicated in the drawing, two FET's 1 and 2 are connected in series between a pulsed power source 3 and a ground level. The gate of FET 1 is connected to drain 3 and the gate of FET 2 is independently driven by a voltage source 4, which receives a pulse after the pulse on source 3 is terminated. The output of FET's 1 and 2 is connected to a terminal of a socket, probe, or other connector 5 by which the elements of FET 6 are contactable.

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Dynamic Cell for Leakage Current Measurement

This described is a test instrument useful in determining the quality of the source-substrate junction in a field-effect transistor (FET). As indicated in the drawing, two FET's 1 and 2 are connected in series between a pulsed power source 3 and a ground level. The gate of FET 1 is connected to drain 3 and the gate of FET 2 is independently driven by a voltage source 4, which receives a pulse after the pulse on source 3 is terminated. The output of FET's 1 and 2 is connected to a terminal of a socket, probe, or other connector 5 by which the elements of FET 6 are contactable. The connector 5 will apply this output voltage of FET's 1 and 2 to the drain and gate of FET 6, will apply a substrate bias voltage B (normally about 3 volts negative with respect to ground) to the substrate of FET 6 and will connect its source to the gate of a measuring FET 7. The bias voltage B will also be applied to the substrates of the other FET's 1, 2 and 7.

FET 7 is a larger FET having its drain connected through a resistor 8 to a voltage supply 9 and its source grounded. The gate to substrate capacitance (c) of FET 7 will have been previously measured for magnitude and will have negligible leakage. The relationship between the voltage on the gate of FET 7 and the voltage across resistor 8 will also have been calibrated by tests. An oscilloscope or X-Y plotter 10 will show the variation of the voltage across resistor 8 with time.

In operation, after FET 6 is atta...