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Browse Prior Art Database

Charge Sense and Transfer Scheme

IP.com Disclosure Number: IPCOM000077330D
Original Publication Date: 1972-Jul-01
Included in the Prior Art Database: 2005-Feb-25
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Berger, HH: AUTHOR [+2]

Abstract

Charge differences on capacitances C1 and C2 (Fig. 1) are amplified and sensed via a flip-flop with loads L1 and L2, which do not provide a discharge path for capacitances C1 and C2 when the flip-flop is switched off the power supply.

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Charge Sense and Transfer Scheme

Charge differences on capacitances C1 and C2 (Fig. 1) are amplified and sensed via a flip-flop with loads L1 and L2, which do not provide a discharge path for capacitances C1 and C2 when the flip-flop is switched off the power supply.

Transistors T1 and T2 are shown in bipolar technology, but, for example, field-effect transistors are equally suitable. With the flip-flop having a good symmetry, very small charge differences on (equal) C1 and C2 are amplified after the flip-flop has been switched on. The sign of the charge difference can be identified by logical signals "1" or "0" and may originate from a storage device.

The storage device may be, for example, a preceding stage of the same configuration as the flip-flop of Fig. 1. With a row of such stages and by providing a proper coupling means, a shift register is realized by alternately switching all the flip-flops with an odd and an even number in this row. Fig. 2a shows such a shift register in bipolar technology and Fig. 2b the associated clock diagram. During stand-by this shift register is statically operated by a low DC current, whereas during shifting the register operates dynamically by sensing charge differences of preceding stages and by transferring them to subsequent stages.

The flip-flop loads are realized by PNP-transistors, for example. NPN transistors T3 and T5 provide the coupling; C1 and C2 are the effective capacitances on which charge differences are built u...